Writing Blockrams in VHDL

Nov 13, 2003 2 Replies
M

Hello,



I need to use a blockram as a FIFO to port data from one clock domain to another. I created a blockram with help of the language template. This blockram is recognised by the XST synthesiser. The dual clock is also recognised after a small modification. The next problem is to describe a databus width conversion. There is a 32 bit processor bus on one side and a



1 bit serial output on the other side. This is no problem with a library element or a blockram instance from the coregen. I don't like the coregen modules because it is not easy to back-up your sources or transport them to another PC. The library instances make the code less portable. Is there a way to describe the width conversion in VHDL without creating extra logic outside of the blockram?

Thanks, Mark



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P

Mark, I cannot help you with the VHDL, but recently having investigated a similar design, here are some issues:

Asynchr>

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M

Thanks Peter for the warnings. We are building a FIFO with normal binary counters, but the empty and full signals are not based on bytes but on 64 byte packets. Therefore there is enough time to get a reliable empty and full indication in both clock domains. We also have the advantage that our clocks are 'slow' (40 - 50 MHz). I have build these FIFO's with success before in other projects, but always with the aid of the core generator or library elements (the latter code is unreadable because 4 - 6 blockrams are instantiated for one blockram)

Mark

"Peter Alfke" schreef in bericht news: snipped-for-privacy@xilinx.com...

frequencies.

and a

coregen

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logic

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