Hi everybody, while I was trying to create a statemachine with registered outputs which shouldn't be delayed by one clock cycle (as usual when just putting a register behind the outputs of the FSM) I modified some sourcecode from the XILINX ISE Language Templates for sythesis. As an example I tried to recreate the stopwatch statemachine from the ISE 5 In depth tutorial.
Everything works fine insofar that the function is correct and itentical to the original design and it also synthesizes fine with one little exeption:
The XST-Synthesis Tool does not recognize my coding style as a FSM, therefore it wont do the neccessary optimizations. For comparision purposes I have added some XST-synthesis report snippets to outline the differences:
While my coding style produces a register and some feedback logic around it, for the original code (Produced by StateCAD) XST inferes a FSM and applies all optimizations on it.
(When I comment out the enum_encoding attributes in my code then register CS will become One-State-Hot encoded, but no OSH-FSM will be created. Instead some clumsy binary FSM with an unreal OSH encoding (all statebits zero!!! - not allowed for OSH encoding!!!) will be generated.
So, what trick makes the XST-Synthesis tool recognize my coding style to be a FSM working in the way I want (that is with registered outputs but no delay by one clock cycle)?
All help is appreciated.
Thanks
Eilert
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- HDL Synthesis * =========================================================================
Synthesizing Unit . Related source file is S:/ssy_laboratory_test/ssy_stopwatch/ELIS_Statemachine.vhd. Found 1-bit register for signal . Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 5 D-type flip-flop(s). Unit synthesized.
========================================================================= HDL Synthesis Report
Macro Statistics # Registers : 3 3-bit register : 1 1-bit register : 2
=========================================================================
=========================================================================
- HDL Synthesis * =========================================================================
Synthesizing Unit . Related source file is S:/ssy_laboratory_test/ssy_stopwatch/STMACH.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 6 | | Transitions | 11 | | Inputs | 1 | | Outputs | 2 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit synthesized.
========================================================================= HDL Synthesis Report
Macro Statistics # FSMs : 1
=========================================================================
Optimizing FSM with One-Hot encoding and d flip-flops.
Sourcecode of elis_statemachine.vhd:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ELIS_Statemachine is Port ( Clock : in std_logic; Reset : in std_logic; StartStop : in std_logic; ClockEnableOut : out std_logic; ResetOut : out std_logic); end ELIS_Statemachine;
architecture Behavioral of ELIS_Statemachine is type STATE_TYPE is (Clear,Zero,Start,Counting,Stop,Stopped); attribute ENUM_ENCODING: STRING; attribute ENUM_ENCODING of STATE_TYPE: type is "000 101 010 001 011
100"; signal CS : STATE_TYPE; signal NS : STATE_TYPE;
begin SYNC_PROC: process (CLOCK, RESET) begin if (RESET='1') then CS ClockEnableOut