Yet another async FIFO question... :(
I've inherited an async FIFO that doesn't work. This is, I think, a fairly standard implementation. On the write port, a clock and a write enable increment a write pointer, and write the write data into a RAM.
The read pointer is Gray-coded, clocked into a reg on the write clock, inverse coded, and then compared with the write pointer, to give a write-side full flag.
The read side is simply the inverse of the write side.
So far, so good. The problem is that this design assumes a free-running write clock, and my write clock is not free-running; I simply generate a clock when the (unpredicatable) write data appears. The write enable is therefore effectively redundant.
The problem arises because the 'fifo full' flag is generated by the
*write* clock. If, on write X, the comparator determines that the FIFO is full, then the full flag is generated, and I don't create any more write clocks. The read side might empty the FIFO, but this information never gets back to the write port, because the register that samples the Gray-coded read pointer is clocked by the write clock.Any ideas on how I re-design this to cope with a write clock which isn't free-running?
TIA -
Paul