Hi,
I just bougth a card with FPGA "Virtex4 XC4VLX60 668pinBGA -11" The board is equiped with a DDR2 SDRAM memorie. FPGA and memory is connected with signals such as DQ[0:15], DQS[0:1], DQSN[0:1]. I use Xilinx controler (MIG 1.72) in ISE 9.1.03i.
The pinout of this board is : DDR2_DQS0 => PIN number M21 (IO_L13P_9) DDR2_DQS0_N => PIN number M2O (IO_L13N_9) DDR2_DQS1 => PIN number K20 (IO_L5N_9) DDR2_DQS1_N => PIN number L19 (IO_L5P_9)
I have an error in ISE, because there is an inversion between DQS1 DQS1_N DDR2_DQS1 should have PIN number L19 (IO_L5P_9) (When I do this inversion in ucf file, I can route my FPGA)
Please, see below the VHDL code (MIG 1.72).
Can you help me to find a solution to modify the VHDL code, and so get round the bug pinout of this board Thanks lot.
Regards, Benoit.
The VHDL code (MIG 1.72) is :
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