I googled around a bit but could not find the answer.
I am using Xilinx Spartan FPGA, with 2 DCM's in series to generate a32MHz clock (50% duty cycle) from a 75MHz input. (First DCM is divide 2.5, second multiply 32 and divide 30).
The first DCM is connected to a system reset via a user pin, and the LOCKED signal of this DCM is used to reset the second DCM.
My question : What is the total lock time i.e. When will the 32MHz clock be available ?
Thanks for any insights,