Data Swtich from LPT to LCD Module!

Hi, I am new to FPGA design. I am now need to make a switch to control the signals from PC LPT to a character LCD module. Right now I am using Altera UP1 demo board for verfication which has

1 MAX CPLD and 1 FLEX fpga. And I write a simple code just like D_out
Reply to
Johnson Lee
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To summarise :-

Test 1: PC LPT-->FPGA-->LCD. FAILS. Test 2: PC LPT-->CPLD-->LCD. FAILS. Test 3: PC LPT-->LCD. No CPLD. No FPGA. Works OK. Test 4: CPLD-->LCD. No PC. Works OK Test 5: FPGA-->LCD. No PC. Works OK.

Is this correct? Did you check _all_ outputs using an oscilloscope in tests 1+2? Was the LCD connected to the same outputs in 1+2 as it was in 4+5? Are you using the Altera Quartus development environment? Could you post sample Quartus archive (.QAR) files?

Reply to
Andrew Holme

Hi Andrew, Yes, you are right about those 5 different tests! And I didn't check all outputs using oscolloscope only Enable pin and some data bits. I can see from oscilloscope when enable pin is initiate, the data pin voltage will sweep between 3.0V to 5.0 when LCD module is switched on, but remain 3.0V when LCD is off. Same IO assignment in those files... Ya, I can show you my code! But I don't know how to do that! Mail the .QAR to you directly?

BR, Johnson Lee

Reply to
Johnson Lee

snipped-for-privacy@itri.org.tw (Johnson Lee) wrote

Those voltages don't sound right. The logic should swing from 0 to Vcc. What power supply voltage are you running the CPLD / FPGA at?

5.0V or 3.3V? What power supply voltage are you running the LCD at? You're not missing a ground connection somewhere are you?

Can you put it on a web server and post the URL? If not, my mail is

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Reply to
Andrew Holme

Hi Andrew, I make a call to local Altera FAE, and he replied that the Vout should be above 2.5V for this FPGA when in high level. LCD module needs 5V power supply, so does the FPGA demo board. I make those measurement again this morning and I see the voltage swing has the same frequency as the Enable signal.. Right now my LPT signals come from a Linux OS system. And the LCD Enable is set to polling every 1 second. I just receive a VHDL code from Altera which show me how to modify the pins into open-drain, and I will try this tomorrow. Also, I will sent you my .QAR files later when I come to office tomorrow..

Thanks for your reply!

BR, Johnson Lee

Reply to
Johnson Lee

Hi Andrew, I already find the bug. It was the software which read the busy flag when system boot up. I am going to modify my code.

Thanks for sharing your time with me discussing this problem!

BR, Johnson Lee

Reply to
Johnson Lee

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