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SPI module in FPGA

I am trying to write code for a SPI circuit (in VHDL) for the Altera Cyclone II FPGA. I think I understand the implementation of essentially what amounts to a shift register. However, what is a good way to deal with the serial clock. The FPGA will act as a master interfacing with a slave A/D converter that supports SPI interface. Thus, the FPGA will need to generate the SPI clock. The FPGA will contain a simple processor implementation. I think the processor clock can be used to derive the SPI clock, but would it better to provide an independent clock for the SPI? If so, what is a good way to do this? I am not much experienced in FPGA design, so any help or references/links would be greatly appreciated.

Thanks!

Reply to
firebird
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firebird =EB=FA=E1:

You can easily generate the SPI clock by deriving it from your main CPU clock, there's no problem with this. Note, however, that you won't be able to have a SPI clock faster than Fclk / 2 where Fclk is your CPU clock. This shouldn't be a problem, as in 99% of the cases SPI communication is slower than processor speed.

Reply to
Eli Bendersky

The clock doesn't have to have any particular duty cycle or frequency (other than below the maximum for the slave). It only has to be exist while you're clocking data around.

If your AD is slow, you'd probably save resources by bit-banging the SPI from your processor. The memory for the code is probably less expensive in your design than area in the FPGA for a real SPI master.

--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

Can you elaborate on "bit-banging" - that is a completely unfamiliar term.

Thanks!

Reply to
firebird

"Bit-banging" or "bit-bashing" is generally used to describe the technique of 'emulating' a communications protocol in software rather than employing a purpose-built peripheral normally used for the task. Typically the I/O would occur on MCU GPIO ports.

Aside from SPI, another common candidate is serial (UART) comms.

Obviously the wire speed must be sufficiently slow to enable software to keep up with the protocol requirements.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Reply to
Mark McDougall

@firebird:

Typically, the "SPI-interface" of ADCs ist nothing more than a shift register carrying out one bit per clock, so it is up to YOU which clock speed to choose. In very rare situations, you will create a unique and isolated design dealing with high speed ADCs and interfacing to the rest of the FPGA. But here, a counter and a bit-BUX should be all to be done. The counter should have a fixed relationship to your CPU master clock (one one clock domain simpler to handle) and an eye should be kept on the timing: Some ADCs respond e.g. on the falling edge of their local clock, and additional timing delays caused be drivers might will cause tricky edge constellations of data and sampling clock. To deal with this, I usually prepare a second clock in the FPGA running at the double frequency and driving the output registers (here ADC-clock driver).

In a recent video design, the ADCs are fed with 100MHz clock speed (full FPGA speed) where the driving clock is passed through register FFs clocked with not200Mhz resulting in 25% additional delay and an perfect timing constellation between data signals and rising clock.

Reply to
alterauser

You might consider looking at an example on opencores.org to get ya start, pretty sure they've got an SPI interface.

As for the clock, you can easily divide down your main processor clk with a few registers, or I imagine the cyclone's have something analagous to Xilinx's digital clock manager, which lets ya do all sorts of fun multiplies and divides and things (with the penalty of some jitter of course).

given the m> @firebird:

Reply to
Paul

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