clock divider

Tell us more about your application. For example, is 7812.5 a fixed number, or will it be varied at "run" time or compile time?

What precision do you need? Does the 7812.5 have to be exact, or is there some tolerance?

How much jitter can you tolerate on the output?

What range of duty cycles can you tolerate on the output?

Whatever. The answer is probably going to involve a phase accumulator, and I'll probably end up directing you to this web site:

Regards, Allan

I have written a divide by 2.5 routine. You could use this followed by a divide by 3125 to give 7812.5 that you require.

--- Divide by 2.5 counter --- entity div2p5 is port ( clk : in std_logic; q : out std_logic); end div2p5;

architecture div2p5_arch of div2p5 is signal cnt0 : std_logic_vector (2 downto 0) := "000"; signal cnt1 : std_logic_vector (2 downto 0) := "000"; signal q0 : std_logic; signal q1 : std_logic;

begin

"Allan Herriman" skrev i en meddelelse news: snipped-for-privacy@4ax.com...

with

The reference that I use is a PPS (pulse per second) signal that has a precision on +/- 50nsec

A small jitter on 12800Hz +/- 1000 ppm is okay but a control loop should remove the jitter when measured over e.g. 1000 secs

Regards Rune Christensen