Hello there
I'm having serious problems configuring my FPGA using EPC2. We have designed the circuit exactly as stated in the Altera datasheet and even played around with the pullups and buffering that's recommended. To be more specific, We have a board with a FLEX10KE (EPF10K200SBC356-1) and a EPC2LC20 for in-system configuration. We also have provided for direct Byteblaster configuration using a connector (using the same path towards the FPGA and selecting between them through enabling/disabling a buffer). Finally, we have a JTAG connector by which we can configure the FPGA directly using the SOF file generated by Quartus - pls read below. Anyway, what we're seeing is: The EPC2 gets progammed OK but then the problems start. When I turn the system off and on again to initiate configuration the nCONFIG pin comes out of reset and so does nSTATUS but only for a very small amount of time. During this time DCLK goes enabled and DATA transfers configuration data, as normally. Then nSTATUS goes low again and the configuration is interrupted as you would expect. There is nothing in the circuit that could pull this pin low - it is a point to point connection between FPGA and EPC2. It seems however that the EPC2 goes back on reset state hence pulling its OE pin low. From that point onwards these signals are going crazy, ie they randomly go high or low so the FPGA never gets configured. Tried using external pullups whilst disabling the internal ones through Quartus, but there was no change. One last point is that so far I've been configuring the FPGA through a direct JTAG connection using the SOF file - this works fine. Does this perhaps confuse the device, ie how does it know whether it should be programmed through JTAG or EPC2. Do I need to set something there? Finally, I'm using the POF file to program the EPC2 - I'm assuming this is correct?? Please give me some feedback because I'm really stuck with this. Any tips would be much welcome. Thanks in advance