Dear Sir or Madam,
when you go to the linked site you see the simulation plots (functional simulation) of the SRAM controller which I am designing for the SRAM CY7C1399B. There are shown the sram_address, sram_data and the control signals Oe_bar, Cs_bar, We_bar for writing to a location and reading from this location later. But when trying to read from that location the data bus is in undefined state ('U'). The reasons could be:
- writing to that address was not done correctly so that the written data is corrupted.
- reading is not done correctly Where could be the problem? I would be very thankful for some useful hint.. Andrés Vázquez
p.s. Do the changed timing constants in CY7C199.vhd take affect when doing a functional simulation ?