SRAM Controller Problems

Dear Sir or Madam,

when you go to the linked site you see the simulation plots (functional simulation) of the SRAM controller which I am designing for the SRAM CY7C1399B. There are shown the sram_address, sram_data and the control signals Oe_bar, Cs_bar, We_bar for writing to a location and reading from this location later. But when trying to read from that location the data bus is in undefined state ('U'). The reasons could be:

  1. writing to that address was not done correctly so that the written data is corrupted.
  2. reading is not done correctly Where could be the problem? I would be very thankful for some useful hint.. Andrés Vázquez

p.s. Do the changed timing constants in CY7C199.vhd take affect when doing a functional simulation ?

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It's hard to tell from the screen dump, but it looks like you might not be meeting the data hold time on writes (from the datasheet it is minimum 0 nS after rising edge of write enable, but in the simulation it might require nonzero hold time to first register the rising edge event. This time would then depend on the simulation resolution)

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Gabor Szakacs

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