Hi newsgroup,
I am trying to write a VHDL wrapper for a Verilog IP core which includes a "params.v" file:
`define DDR2_MODE `define ROW_WIDTH 13 `define COL_WIDTH 10 `define COL_WIDTH_EQ_10 TRUE ...
These parameters are used to define the port widths etc. of the IP core.
How can I take over the parameter file into my VHDL wrapper ? Do I have to generate a second VHDL parameter file ?
Thank you for your opinion.
Rgds Andre