I am working on synthesizing some legacy code, and Synplify (correctly) finds a combinatorial loop in the logic. My gut reaction was to modify the function to use a latch instead of a feedback path because I've always been told that combinatorial loops are bad practice for ASICs / FPGAs. After completing the redesign, the new circuit takes up at least twice as much space as the old one and it is difficult to exhaustively verify that the re-implementation preserves the functionality.
The combinatorial loop implementation is in a product, and has been working without problems (presumably) for years. So the question I would like to present for discussion is:
Why is it so bad to use combinatorial loops? What are the potential pitfalls?
I would be interested in hearing this issue addressed from an ASIC design point of view as well.
For reference, I am including below a testbench I created to test the various implementations. The first two process represent the original implementation and create the OutA output. The 3rd and 4th processes represent the latch based implementation. The 5th process is an (almost) exhaustive testbench to verify that the two implementations behave the same way.
Thanks
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL;
ENTITY test IS END ENTITY test;
ARCHITECTURE test_arch OF test IS
SIGNAL Latch : STD_ULOGIC; SIGNAL In0 : STD_ULOGIC; SIGNAL In1 : STD_ULOGIC; SIGNAL In2 : STD_ULOGIC; SIGNAL In3 : STD_ULOGIC; SIGNAL InternalSig : STD_ULOGIC; SIGNAL OutA : STD_ULOGIC; SIGNAL OutB : STD_ULOGIC; SIGNAL TestVector : UNSIGNED(3 DOWNTO 0);
BEGIN
proc1 : PROCESS (In1, In2, OutA) IS BEGIN IF (In1 = '1' OR (In2 = '1' AND OutA = '1')) THEN InternalSig