Hi Group,
Just wondering if anyone has seen this issue. I am simulating a Xilinx FPGA design (RTL) containging DCMs. I get the following warning
Warning : Input Clock Cycle Jitter on on instance * exceeds 0.3 ns Previous CLKIN Period = 0 ns Current CLKIN Period = 13.33333 ns
On the face of it, the meaning of this warning should be clear *but* there is definitely no jitter on this input clock. It is driven directly from a testbench. i.e. The warning is completely wrong.
I am using cadence ncsim (mixed VHDL/Verilog). This DCM model is VHDL.
Has anyone seen false messages like this? Did you find a workoround or good explanation.
Thanks,
Steven