synchronous reset problems on FPGA

I prefer an asynch assert for simulation of the 'no clock running' case.

I generate an asynch assert and sync de-assert reset strobe, something like this.

It's just a two flop shifter, reset_out is preset with reset_in. A zero is clocked out to de-assert reset_out.

I would clock all the flops at the original clock speed, reset everything the same way, and use clock enable strobes for the slower update rates.

-- Mike Treseler

Hi Mike,

thanks for your input. When you mean clock enable strobe, do you mean... the following?

process (clk) if clk=1 and clk'event then if res = '1'

else if clock_enable = '1'

end if; end if; end if;

--then clock_enable will be in my case asserted one in every 4 clocks to achieve a f/4 MHz kind of data rate...

If my understanding is correct, then I have another question. The maximum synthesizable frequency of a core used in the design cannot run at clock speed and only at 1/4 clock speed. currently, I have thus

1) 1 clock runnning at f MHz

I have prevented potential clock domain crossing problems by piping data already into an async FIFO (data entering the design written into the FIFO at f MHz, data read out at f/4 MHz which goes into the core also clocked at f/4 MHz).

Since you advised to use the strobe method as I understood above, then how do i go about clocking the core that can run at only f/4 MHz max and still not run into the reset problem stated above?

thanks again for your help. Chris

If you use a global clock to distribute the fast clock, but us CE to disable each flip-flop for 3 out of 4 clock ticks, then that part of your design really runs at the quarter clock speed. The flip-flops see only every fourth clock tick, therefore your design will work as you expect. Peter Alfke

There is only one clock domain. The reset circuit is separate. See Peter's answer. Post to comp.lang.vhd if you don't figure it out.

-- Mike Treseler

Hi Peter, I do not have this luxury. The core which is running at f/4 clock is a core originally written in Handel C and given to me as a ngc file and not in VHDL. The maximum synthesizable speed of this core is only at f/4 MHz. The core thus has to run at an f/4 clock. With this set of restrictions in mind, could there still be a solution to the reset problem?

Chris

There must be a limited number of flip-flops in that part of the design. Just clock each of them with the fast clock, and drive CE with the slower clock. And forget all about asynchronous FIFOs. Do you understand hardware, or are you just patching cores together ? Peter Alfke

Hi Peter, I understand exactly what you are saying. Unfortunately I am just patching cores together. As mentioned, what I get is an ngc file which I do not have any control of the core.

Chris

I believe this only applies to Xilinx FPGA's and not to any other vendors.

From

Use of Synchronous Sets/Resets If a set or reset is necessary for the proper operation of the circuit, a synchronous reset should always be coded. Synchronous sets/resets not only have improved timing characteristics and stability but can also result in smaller, better utilization within the FPGA. Synchronous sets/resets can result in less logic (fewer LUTs), fewer restrictions on packing, and, often, faster circuits.

Hans

There is an obvious answer that nobody seems to have mentioned: Use the "LOCKED" signal from the DCM as reset to the logic that is clocked by the clock from the DCM. I am not quite sure about the numbers, but there ought to be at least one clock edge from the DCM before that goes active. If you need more clock edges, delay the "LOCKED" signal in a shift register (one SLR16 will give you 16 clock cycles delay from just one LUT).

Hope this helps!

/Lars

Mike mentioned this in his first post but you seemed to have missed the point with the diversion down clock enable lane. The reset to the block that you're trying to control should not be the same signal as the reset to the DCM. Instead...

1. Take the reset input to the DCM or it together with the DCM not locked output to create a new signal that is used to asynchronously preset a shift register.
2. Clock the shift register with the DCM output clock (i.e. the clock / 4).
3. Use the output of the shift register as the reset to the block that you're trying to control.

The shift register output will now be properly synchronized to the 'clock / 4' clock domain and will be nominally active for as many clock cycles as you make the shift register. Add one extra flop to the shift register to account for not knowing precisely when the reset input to the shift register will go away (i.e. to get a minimum 1 clock cycle wide reset, make the shift register 2 flops long).

Kevin Jennings

Peter, from what Chris has said I don't think there are CE's into the core he's using.

Nial

Yep, the DCM locked output does the trick!

-a