Stratix & PLL

Hello,

I have a problem with Stratix's PLLs. I want to feed input of Enhanced PLL from Fast PLL and Enhanced PLL form Enhanced PLL.

CLK input -> Fast PLL -> Enhanced PLL -> PLL output -> other logic or CLK input -> Enhanced PLL -> Enhanced PLL -> PLL output -> other logic

Is this two configuration possible to achieve in EP1S25 device?

Quartus 3 signalize errors when I am trying to do that: "Error: inclk0 port of PLL interface_block_hes:INB|hes_plla:u2|altpll:altpll_component|pll must be driven by a non-inverted input pin or, in a fast PLL, the output of a PLL".

Regards, Krzysiek

Reply to
Krzysztof Szczepanski
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Hi Krysztof,

The connections described in your post are not possible with the Stratix architecture.

- Subroto Datta Altera Corp.

PLL".

Reply to
Subroto Datta

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