Dear Gurus;
I have 1 Cyclone IV GX EP4CGX150(DF27C7) This Cyclone IV is connected to 6 x Cyclone III (C40F484) All of these 6 Cyclone IIIs will send 4 bit LVDS serialized input data and a clock(120mhz) I need to deserialize 4 bits of data with their respective clocks by Cyclone IV GXEP4CGX150
Questions
1- Which banks should I use for these 30pins (4 bit data and clock inputs) x6
2- What is the number of PLLs that I need to use while desialization
PS: I used to do this with Xilinx Spartan 6 but I am new to Altera.