I am using an altera cyclone, and want to use the internall pll to divide by 10 a clock. The megawizard plug in manager (form quartusII 4.1 SP2) give the following error messages : "Cannot implement the requested pll, cause : post divider max count exceeded" but the divider counter should be 10, and it possible values are from 1 to 32. So what is the problem ?
1
What is your input frequency?
My input frequency is 20 Mhz... and my output would be 2Mhz
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Read chapter 6 of the Cyclone manual.
fout = fINx(M/(NxG0)) and fVCO = fINx(M/N)
now M can be from 2 to 32 and N and G0 from 1 to 32. fVCO must be between 300 and 800 MHz. since fIN is 20MHz M must be at least 15 when N = 1. Other option is M>=30 and N=2.
fOUT is desired to be 2MHz thus G0 must be 150 when M=15 or 300 when M = 30 so this is not possible...
If you want to divide 20MHz by 10 you'll need a counter to do that. Just count from 4 to 0 and on 0 alternate the outputclock and start counting again from 4.
Hope this helps, Jan
Jan De Ceuster a couché sur son écran :
thanks a lot, i am now less stupid than yesterday ... :D
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