Hi,
I have the following problem:
My FPGA has an input clock CLOCK30. This clock comes from an external transceiver.
The clock CLOCK30 is used as the input clock of a PLL which generates a fast clock CLOCK90 whose period is a third (90MHz).
For my FPGA controller I need CLOCK90 to be in phase alignment with CLOCK30.
CLOCK30 is also used to clock the data into the external transceiver. (clock name at FPGA output pin (CLOCK30_OUT)
So how can I manage that CLOCK30_OUT is in phase alignment with CLOCK30 and CLOCK90 ?
I am using Altera Cyclone Device with its PLL.
The paper "AN251 : Using PLLs in Cyclone Devices" does not show anything about aligning phase relationship of clock input pin, clock at register clock port AND clock output pin"
I would appreciate your help.
Kind regards