Dear friends i am now converting synplify project to the Xilinx environment. I need help on the constrain conversion from Synplify 7.5 to XilinxISE6.2i.
- What is the equivalent constrain of the "defineinput_delay" and "define_output_delay". is "pad to setup" delauy in the Xilinx is equivalent to this. Also there is a refeence to the clock in the constrians.
Sumesh