We have multiple Xilinx FPGAs on our jtag chain. The main VP20 ppc is loaded first. It detects what other cards/FPGA plug into the system, connect those devices to jtag chains and load their ace files.
Everything works fine except when we start to the
-jprog options on the secondary loading of line card/fpga's ace files.
It seems that we the load the line card's ace file (build with -jprog flag), the main FPGA/ppc's configuration memory also being clear.
It looks like the genace's -jprog option is not just for the selected device but impact all the devices in the jtag chain when it programs.
Does anyone know if this is the correct diagnostic of our problem?
If so, we really need to clear the secondary device's configuration memory when we do upgrade those device without power cycle the system. What's the best way to do that?
Thank you very much.
-Tony