I am looking at developing high speed (200MHz+) DDR interfaces for Xilinx or Altera devices. I am wondering if people have thoughts on the best tool flows for achieving such designs.
More specifically: I think I have a reasonable understanding as to how to do fast pipelined designs as far as core logic goes. My concern is how good are the tools at letting you do low-level I/O design? In order to obtain 200MHz DDR rates (400Mb/s data) the designer needs to pay a lot of attention to actual routing paths. Do the current Altera/Xilinx tools provide this level of flexibility/control? Would I be advised to use 3rd party tools (Mentor, Synplicity, Synopsys etc)?
Are these tools good enough for the required static timing analysis, or do I really need to go to Primetime or some other STA tool?