Tools for developing high-speed interfaces


I am looking at developing high speed (200MHz+) DDR interfaces for Xilinx or Altera devices. I am wondering if people have thoughts on the best tool flows for achieving such designs.

More specifically: I think I have a reasonable understanding as to how to do fast pipelined designs as far as core logic goes. My concern is how good are the tools at letting you do low-level I/O design? In order to obtain 200MHz DDR rates (400Mb/s data) the designer needs to pay a lot of attention to actual routing paths. Do the current Altera/Xilinx tools provide this level of flexibility/control? Would I be advised to use 3rd party tools (Mentor, Synplicity, Synopsys etc)?

Are these tools good enough for the required static timing analysis, or do I really need to go to Primetime or some other STA tool?



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I'm doing a lot (40Gb/s total) of 622Mbps I/O in my current Xilinx FPGA design, using XST and STA.

The source code is a mix of RTL and instantiated primitives. Each I/O pin is connected to a RPM, and each RPM is LOC'ed in a UCF to a fixed place on the die. (I would have done it all with RPMs in the source code, but I'm using Verilog.)

I was getting occasional "bad builds" until I did some hand routing, although there isn't much of that. The hand routes were done in FPGA editor, and copied into a UCF.

Regards, Allan.

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Allan Herriman

Hi Greg,

You can achieve 200 Mhz (400 Mb/s) DDR in Stratix, Stratix GX, and Stratix II devices. Stratix incorporates dedicated routing and registers for DDR interfacing, which takes the guess work out of the routing part of a DDR design. You can successfully develop your own DDR interface with Quartus and any synthesis tool (or integrated synthesis), and you do not require 3rd party STA for this. However, if you choose to go this route (rather than using an IP core), I would carefully read all available documentation on DDR and it probably wouldn't hurt to talk to an Altera FAE. They can provide you with guidance to help you properly analyse your DDR timing using Quartus.

We also provide the DDR SDRAM MegaCore, an IP block you can integrate into your design to further simplify the process of interfacing to DDR memories. The MegaCore is available for free evaluation on the Altera web site. There are also links to 3rd party IP cores that provide DDR interfacing capability.

Some references for you:

DDR I/O Signaling in Stratix & Startix GX Devices:

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DDR SDRAM Controller MegaCore

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Paul Leventis Altera Corp.

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Paul Leventis (at home)

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