Hi, I'm attempting to implement a 12-bit counter from a vhdl file using the lpm_counter. The output count goes something like this 125..126..255..128..129 That is, bit 8 (output[7]) goes high one clock cycle too early. The same thing happens when bit 9 (output[8]) goes high, this time the count is as follows: 251..252..509..510..383..256..257..258 Once again bit 8 goes high one clock cycle early, and bit 9 changes 3 cycles early.
At first, I noticed this and assumed there was a problem in my logic driving the counter. Using Quartus, I created a new 12 bit counter using the mega-function wizard and placed it next to my vhdl component. That counter has the exact same glitch. sclr and sset are grounded, updown and cnt_en are connected to vcc. The only input is a clock. Next I completely removed my component, and the counter still has a glitch in the output. The entire .bdf file is a counter with an input clock and output lines, the glitch remains.
Next, I created a new project, re-created a counter, and of course this one works flawlessly.
It seems that no matter what I do, I can't make the broken counter work correctly, nor break the working counter by adding my component to it.
Has anyone experienced something similar to this before? Any ideas on how to fix it?