is there a possibility to create bidimensional array, and do things such as :
signal foo : STD_LOGIC_???(1 downto 0, 7 downto 0); signal foo1 : STD_LOGIC_VECTOR(7 downto 0);
[...]foo(0)
is there a possibility to create bidimensional array, and do things such as :
signal foo : STD_LOGIC_???(1 downto 0, 7 downto 0); signal foo1 : STD_LOGIC_VECTOR(7 downto 0);
[...]foo(0)
There is an example for a bidim array declaration :
type bidim_array is array (width-1 downto 1, width-1 downto 0) of std_logic; signal MEM : bidim_array;
Moti.
Le 25/01/2005, Moti a supposé :
yes, but i can't do something like MEM(i)
Usually I write something like:
ARCHITECTURE ex1 OF example IS TYPE mem_cell IS ARRAY (0 to 1023) of std_logic_vector(0 to 31) ; SIGNAL mem_inst : mem_cell;
and then you could pick the value you want as:
o(0 to 7) > There is an example for a bidim array declaration :
kcl a couché sur son écran :
yes... why ?
-- Ceci est une signature automatique de MesNews. Site : http://www.mesnews.net
Il se trouve que kcl a formulé :
but i should create a new type for any array of different size ...
-- Ceci est une signature automatique de MesNews. Site : http://www.mesnews.net
">>
Parceque c'est plus facile de s'expliquer en francais ;) except if you prefer english or if there is a rule that specify that all post must be in english
PS: Sinon je vois pas d'autre facon que de creer un nouveau type à chaque fois (attention je dis pas que ca existe pas mais juste que je connais ps d'autre facon de faire)
Tu fais du vhdl pas du C :)
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.