Hi
FPGA : Spartan-3, Xilinx ISE :tools ------------------------------------ have wrote a VHDL code to implement shift registers
as shown below
type reg_array is array(7 downto 0) of std_logic_vector(7 downto 0);
signal reg : reg_array;
process(clk) begin if(clk'event and clk = '1')then if(en = '1')then reg
"bijoy" schrieb im Newsbeitrag news: snipped-for-privacy@webx.sUNCHnE...
the logic is that ISE can auto map to BRAM is ver limited and specific, read the datasheet and manuals it is explained there what type of logic can be auto mapped to BRAM
antti
Hi
I have read that, it says we should not use asynchronous reset
The program what i have written is also taken from there and they say it will be mapped to BRAMs
I am observing in my p&r report that it is getting mapped to BRAM but the slice count is not getting reduced.
regds bijoy
be mapped to BRAMs
slice count is not getting reduced.
Hi I don't know how to implement a shift register using BRAMs. That is why i tried to use the map property to enable the mapping option.
If any one has an idea, could you please share it with me.
regards bijoy
Have something to add? Share your thoughts — no account required.
Ask the community — no account required