VHDL simple question: is 2-D array synthesizable

Jimmy a écrit:

Not as such, IIRC. Note that your array is not a 2-D array but an array of arrays, which is synthesizable.

You can but not as you did (see below)

You declared ChipBuffer type with ascending range, you must use an ascending range when using signals of type ChipBuffer: ChipBuffer_I2(1 to 87)

Thanks a million to Nicolas Matringe !!!, solve the problem according to your suggestion :-) , Jimmy,

I have Verilog and VHDL code which has 2D array. They are synthesized correctly with Xilinx XST. But it won't compile with Altera MaxPlus II.

Hendra

Hendra,

Max II has no RAM in the logic plane, so it only seems natural that a 2D array (which looks like RAM) would not be easily recognized.

One should be able to use each LE as a FF in the array, but that is pretty inefficient, and would chew up all resources pretty fast.

There is user flash memory available, and perhaps the synthesis tools require special directives to use it.

What Xilinx parts "synthesized correctly?"

Just curious.

Sounds like a FPGA application, not a CPLD application.

Aust> I have Verilog and VHDL code which has 2D array. They are synthesized

I just tried to inferred a RAM with 2D array

reg [7:0]q[7:0]; //two dimensional array.

In the synthesis report, it said "Found 64 bit register" or something like that! It worked in the Xilinx FPGA exactly the way I want it, which is an 8x8 RAM.

Hendra

I think the OP is referring to the Max Plus II (which I tend to abbreviate to MP2) tool, not the MaxII devices. IIRC the MP2 VHDL compiler can't do 2d arrays (and indeed many other things). Quartus probably can.

Indeed that would happen if the tools recognised the array - if you instantiate an LPM_RAM this is what will happen in devices without RAM blocks (like the old Flex 6K)