Xilinx Engineering Samples

I've got several boards from Memec-Insight with the Virtex 4 LX-25. Unfortunately they are marked "Engineering Samples", which worries me.

Can some one from Xilinx explain the difference between Engineering Samples and Production devices ? Are there any function/electrical/ timing differences ?

Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

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Rudolf Usselmann
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Rudi,

You must download the XC4VLX25CES errata datasheet, find out what the short comings are, and decide if they matter for your application and evaluation. Unfortunately, the Xilinx web site uses session specific dynamic links, so this is as close as I can get an exact url to point you to the pdf for the ES. Go to the errata section at the bottom of this page:

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This datasheet describes some JTAG specific issues that may be the root cause of your other post. More power requirements during init -- check your power supplies!

Thanks, Steve

Reply to
Steve

Let me give a more generic answer about ES. "Engineering Samples" is really an inappropriate name, I would call it "Early Silicon" :-) The devices are thoroughly tested and perform according to the data sheet, as amended by an errate sheet. By definition, ES parts have an errate sheet (at best it says:"NO ERRATA") We call them ES because some long-term reliability qualification tests have not yet been completed. We might also have to change some masks to fix the errata problem(s). We therefore suggest that ES parts not be used in your final manufacturing. But any idea that ES parts are flakey, not completely tested, or unreliable is dead WRONG. Hope that helps. Peter Alfke, Xilinx Applications

Reply to
Peter Alfke

And a little later...

Hmm...

First you say that "some" ... tests have not yet been completed, and then you say "not completely tested ... is dead WRONG". I hate to quibble, but you ain't having it both ways... :-)

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Reply to
Tobias Weingartner

Tobias,

There is a goal that we must reach to call the product 'production' in terms of test coverage.

So, let us say that ES might be 99.997% covered, but the goal is 99.998% (these are not the actual numbers, but are representative of the differences we are talking about).

Aust> Peter Alfke wrote:

Reply to
austin

tests

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Reply to
Peter Alfke

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What is the likelihood that the "errors" in the errata will be fixed for the production devices for the V4LX25 ?

rudi ============================================================= Rudolf Usselmann, ASICS World Services,

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Reply to
Rudolf Usselmann

Peter,

According to the errata there seem to be some serious problems with some of the ES parts. I would assume Xilinx would strive to fix those ? Or am I wrong ?

Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

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Reply to
Rudolf Usselmann

Then I would not care at all and just make something up ;-)

Kolja Sulimma

Reply to
Kolja Sulimma

Rudi, I have no association with Xilinx, so I suggest you develop a contact with Xilinx to get a real answer. Getting the inside "what and when" story on fixes is unlikely to be revealed in this forum, due to what should be obvious competitive reasons.

In all fairness, Engineering Samples are early version product that many manufacturers ship to get something in the hands of their customers so that they can hopefully get a major portion of a design debugged before the final product is available. I've been glad to get ES parts, given the alternative of waiting. Typically the errata is corrected in the final product, but there is no guarantee. My experience with ES parts has been that the issues can be worked around or put off, so that I can complete >90% of my design with the ES parts. However, if one of the errata issues is critical to your application, you are screwed. Maybe I've been lucky. YMMV, buyer beware, do your home work.

The errata datasheet seems to suggest a higher initialization current draw with this ES part, though I may be jumping to conclusions, since I've _not_ even looked at this part's full datasheet. (I've personally seen higher current draw for ES parts during init with a competing FPGA manufacturer who's name begins with "A," so it is my knee jerk reaction.) It is certainly an easy check for you to confirm that you are not experiencing some sort of power supply glitch during init. Instability would not be unheard of if LDO regulators are being used, for example.

Good Luck, Steve

Reply to
Steve

All,

Yes, these ES errata issues have been addressed on the LX25.

There is a 'zeroization' current (~400mA) on Vccaux as the part cleans out the config memory that just sticks, and doesn't go away on the very first LX25's, until they are configured. All other parts have fixes for this, so the LX25 will get its fixes, too. In a fixed part, there is still a 1-4 ms period of increased Iccaux, but I would hardly call it a surge, as it is on the order of a few hundred milliamperes, which the part will need anyway if DCM's are used (as well as the other circuits that use Vccaux).

If the minimum Iccaux (per the data sheet) is provided, everything works just fine.

The TDO issue is also fixed.

For more details, you mail email me or Peter directly. I am presently not in San Jose until Friday.

Aust> Rudolf Usselmann wrote:

Reply to
austin

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