I am trying to synthesize this piece of code entity Coin is Port ( reset : in std_logic; quarter : in std_logic; dime : in std_logic; nickel : in std_logic; isselvalid : in std_logic; d2 : out std_logic_vector(3 downto 0); d3 : out std_logic_vector(3 downto 0); coinval : out integer range 0 to 95); end Coin;
architecture Behavioral of Coin is signal temp : integer range 0 to 95; begin
process(reset,quarter,dime,nickel,isselvalid) begin if reset = '1' then d2
[...]
pulse. I
aHowdy, uhhh...wizz,
First off, you're looking for comp.lang.vhdl, not comp.arch.fpga. But since you're here...
I'll assume for the moment that you wrote the above code and your prof didn't give it to you and say "what is wrong with this code?"
Try to draw the above circuit on paper - notice a problem with the nested FF's? So now your job is to figure out how to write the process such that it uses one clock (hopefully you have a free-running one), yet is able to handle all three token types. Again, draw the schematic on paper first... then find the HDL to describe the circuit.
Have fun,
Marc
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