Re: Input comparator

Luiz,

The input comparator is not characterized as a general purpose comparator, but it actually is pretty useful in that way.

There is some samll offset voltage from the mis-match between the differential pairs (both nmos and cmos to cover the voltage range). I do not know what this offset might be, but I suspect it is less than a few tens of millivolts, worst case from the transistor models.

The comparator will switch as soon as the voltage is greater than the offset (we spec 100 mV for speed reasons, not because it needs > 100 mv to function).

So with 50 mV it will switch, just more slowly than if it was 100 mV.

Aust> Peter, Austin!

Maybe they can shed some light, but using a digital circuit for analog functions is like trying to use a car as a tractor. It might work but it sure as heck wasn't designed to plow fields - you're bound to have problems.

Since digital logic has fixed thresholds and large noise margins (difference beteween Vih and Vil) there's no need for the designers to be detailed about keeping the internal noise to the sub-millivolt level when there's so much activity in the adjacent I/O cells or internal logic.

The Vref pins on the bank are designed for I/O signalling where the threshold does not change so dynamically changing this value dramatically can have unforseen effects.

LVDS signalling produces the best differential capability, allowing a dynamic "Vref" for your doomed analog comparator in the digital device but the noise margin for LVDS is still a rather large value.

If you put nothing else in the FPGA, I imagine you could get good noise-free results with a consistent transition (though subject to an offset voltage in the many 10s of millivolts). My guess is you want more than just the analog comparator in there.

Consider using... an analog comparator!

- John_H

Hi Luiz, I'll try to comment.

I see other numbers in document "Spartan-II:DC and Switching Characteristics" (table on pg.3). Inequations should be as following: Vout = low, if Vin = Vref + 0.1(volts, here and below)

Suppose Vin=Vref+0.02 in your question to match corrected inequations. Vout will not go high. As you are breaking the logical input level requirements hence the input buffer will behave like non-linear differential amplifier (so it is always possible to find such Vin value on DC input-to-output transfer curve that Vout will stand between Vhigh and Vlow, say Vout=(Vhigh+Vlow)/2+Voffset and this point will be stable if Vin is stable).

I don't think this is about metastability unless you bring positive feedback to input buffer.

This is only my opinion, I can't verify it with measurements, unfortunately.

Regards, Andrey

Hi Austin.

First, as Andrey pointed out, I took the wrong table. The best values are for GTL: Vout = low, if Vin = Vref + 0.05

I really would like to know what this offset is and to have a speed versus offset formula.

But, let's suppose we didn't reach the offset value. If we range Vin from Vref-Voffset to Vref+Voffset, I think Vout will range from Vlow to Vhigh monotonically, maybe almost linearly. Am I right?

Now, if we sample Vout with the input data flip-flop, FF DOUT will be

0 or 1 (forget about metastability for now). Can I say there is Vthr where: if Vout>Vthr then DOUT=1 and if Vout

Yes John. But, if I can have one for free, why not use it? Even if it doesn't fit my needs, the knowledge remains.

Luiz Carlos

Luiz,

Last things first, the LVTTL input does not use the comparator(s) (there are three different comparators, as well as other ciruits for the various input standards).

The comparator is designed to have a relatively high gain, so that it switches quickly.

As I said, the offset voltage is due to the Vt mismatch on the pmos and nmos diff pairs, and since these are built with .35u (VII) or .25u (VII Pro) transistors, they are pretty darn fast diff-amps. There is a classic gain stage after the cmos diff-amp (similar to the ones in "CMOS Circuit Design, Layout & Simulation" by Baker, Li, and Boyce). The offset voltage is typically less than a few 10's of mV (say 10 to 20 mV worst case). I am sure that if you vary the voltage difference slowly enough, you could measure the gain of the diff-amp. It was designed for HSTL and SSTL IO standards, which as someone already pointed out, are pretty sloppy. What I will point out here, is that I am not aware of any monolithic separate comparator that is as fast as the one that is in the input circuit. This comparator is good for

400 Mbs+ speeds, which is a lot faster than most separate IC comparators....

Aust> Hi Austin.

John,

Uh, it is an anolog comparator....just one optimized for HSTL and SSTL inputs.

Comments about noise are well put, and need to be considered if the comparator is on the same chip, on the same board.

But to imply that we could somehow be sloppy, and design a crummy comparator is a bit unfair, the comparator is probably much better than any single device you could name, it is just that we did not characterize any more than we had to.

Aust> > Peter, Austin!

Thankyou Austin.

I'm thinking of using this internal comparator for a Delta-Sigma ADC.

Luiz Carlos.

Luiz,

We have done this, and it works. The question is how well? The answer is that we have never actually used this in a system where other things are going on as well, and then measured the S/N of the ADC, resolution, THD, etc. Let us know how it turns out. Better than using Vref and the input would be to use an LVDS input buffer (as was already pointed out) differentially. You will only get a good 1V to 1.5V span (where the comparator works the fastest and best), but the differential input leads to less noise.

Aust> > Luiz,

On a sunny day (Thu, 04 Sep 2003 07:41:43 -0700) it happened Austin Lesea wrote in :

we have never

then measured the S/N

using Vref and the

differentially. You will

best), but the

So with say 10 mV and a 1 V span, is 1 in 100, and that speed, put a R2R on some

8 output pins, and do succesive aproximation to create a video ADC? For a span of 2.5 V you would get 8 bits... That would be usable. At 400Mbs / s in 8 steps would be 50 MHz Do I understand this right? (Non linearity could be corrected in software, maybe the gamma would be good hehe:-) ?

Jan,

You could resolve finer than 10 mV (offset does not equal resolvable step size), so that the resolution is limited more by the noise, and response time.

And all of the self-calibraing tricks used in modern ADCs could be used here as well to improve the linearity and the response.

Aust> On a sunny day (Thu, 04 Sep 2003 07:41:43 -0700) it happened Austin Lesea

that we have never

then measured the S/N

using Vref and the

differentially. You will

best), but the

some 8 output pins,

hehe:-)