Hello,
I recentally purchased a Stratix II (60) DSP Dev Board (from Altera) and I have been having a bit of trouble getting the ADC to work correctly and I was wondering is there was anyone therer that had experience with this board.
I am able to get it to work when the clk is set to 100MHZ, but is I use a PLL to run the clk at say 80MHz then the data that I read from the ADC (also clocked at 80MHz from the same PLL output) is not clean. i.e. it is similar to the signal I would expect however it has spikes in it everywhere. I assume this is a clock skew issue or something like that. I have found that if I use a seperate PLL output to drive the ADC clk then I apply a 180 degree phase shift to that output then my data looks clean.
So the questions I have are:
1) It would appear that you need to apply a phase shift on the adc clock output to account for clock skew (or for some other reason). How do you decide by how much to phase shift the clock? I chose 180 degrees at random and it seems to work, however I am concerned that this was not a very academic approach and I could be near a threshold of working / not working.2) It appears that my data is inverted, does anyone know if the ADC's on this board are active high or active low? I had assumed active high as there is no _n suffix next to the pin name, but my data does appear to be upside down.
Regards
Paul Solomon