Compensated clock in Stratix

hi,

I want to know what is meant by clock compensation and which clock in the design should be compensated or used as compensated clock and advantages of doing so in an enhanced pll.

Reply to
banesh
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Clock compensation refers to using the PLL to align the clock at some point in your design with a reference clock edge. Typically the reference clock comes from an input IO in your design.

The most common compensation is to align the clock edge that the FPGA registers receive with the clock edge of the reference clock. That means the PLL is compensating for the delay of the global clock network used to reach those registers, by generating a clock that is earlier in time by the same delay as the clock network.

The enhanced PLLs in Stratix have several compensation modes:

Normal mode: compensate for the delay of a clock distributed on a global network -- chip-wide global or regional (quadrant) global.

Zero delay buffer: Compensate for the delay to an output IO. Generally used when you want to send out a clock to your board that is phase-aligned to the input clock (i.e. has no delay versus the input clock).

External feedback: Lets you take the clock signal out to your board via an output IO, and send it back into the Stratix chip via an input IO. All the delay in this path will be compensating out by the PLL.

No compensation: Don't shift the clock back in time to compensate for any delay.

What compensation is best depends on what you're trying to do. Normal is the default, and if you have no reason to believe you need one of the other modes, then you should just leave the compensation at the default.

See

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for more details.

Hope this helps,

Vaughn Altera

Reply to
Vaughn Betz

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