Hi Folks, It's been a while since I've needed to do anything fancy with Xilinx timegroups, but I've inherited a design that requires multi-cycle timing constraints. It's a typical scenario, an 80MHz global clock, w/ a 10MHz clock enable active on the 8th phase of a three-bit divide counter. Quoting from the cgd:
"You can place TNM on any net in the design. The constraint indicates that the TNM value should be attached to all valid elements fed by _all_paths_that_fan_forward_ from the tagged net. Forward tracing stops at FFS, RAMS, LATCHES, PADS, CPUS, HSIOS, and MULTS." (emphasis mine)
After inserting the proper grouping constraint:
NET "CE_10MHz" TNM = "TG_10MHz"; # FFs, RAMs, etc that operate w/ 100ns period
what I see in Timing Analyzer is that the group TG_10MHz appears to be limited to only elements that are directly on the CE_10MHz net, and combinatorial derivatives ( specifically, conjunctive derivatives, ie. through an "and" function ) seem to be omitted from the group. To me, the phrase "fan forward" in the doc means through combinatorial logic, not just through routing fabric, and my poor old memory recalls that TNM used to work that way. Consequently, when I apply:
TIMESPEC "TS_10MHz" = FROM "TG_10MHz" TO "TG_10MHz" "TS_Clk80MHz" * 8;
many of the paths that should prioritize into this constraint do not, and are being held hostage to the 12.5 ns master clock period instead of the desired 100ns. Anyone seen anything like this recently?
Regards All, Just John