Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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XC3SD3400A Coprocessor Module
Also new this week is our XC3SD3400A Coprocessor module. Not surprisingly it is based on a Xilinx Spartan-3A DSP XC3SD3400A FPGA. Module has JTAG, SPI configuration and a 6A core voltage regulator as...
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12 years ago
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Raggedstone3 - Altera PCIe Development Board
If you didn't see it already in our our newsletter we have a new PCIe devopment board based on an Altera Cyclone-IV GX. The new board keeps most of the mechanicals and features of our Raggedstone...
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12 years ago
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Synplify compile points keep getting resynthesized
Hi all, For some reason synplify is resynthesizing my compile points even though the compile points' rtl have not changed and compile points' sdc files are the same as the initial compile. Synplify is...
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12 years ago
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question about vtr
dear all, I want to run scripts in "vtr_relase/reg_test/script". but I could not run them, I don not know how I can pass parameter. is there any one to help me ? thanks,
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12 years ago
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Xcell Journal issue 75 now available
We've now published the spring 2011 edition of Xcell Journal (issue 75), which a cover story on Xilinx's new Zynq-7000 EPP family (boots from an ARM Cortex A9 MPU core) and several great features...
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12 years ago
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Re: Xilinx ML605 Demo Qusstion
d The web team fixed the broken link that is used in all of board documentation: will now redirect to the correct location. Ed McGettigan -- Xilinx Inc. AI Inference Acceleration From concept to...
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12 years ago
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Re: Ralph Lauren polo
freelance writer
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12 years ago
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Re: same RTL on two same boards giving different behaviour
packet= ok thanks a lot =) --------------------------------------- Posted through
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12 years ago
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why holdtime is not considerd for Tclkmax calculation
Hi ALL, i just wanted to know why hold time is not considered when we are calculating the Max Frequncy of the sequential design. we only consider the Setup time while doing the Max freq.... Tclk>...
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15 years ago
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DVI to BT.656
Hi All, Has anyone tried to convert DVI format to BT.656? Is there any IP or Reference design available for this? Regards, Akshat
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15 years ago
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Re: ANNOUNCE: TimingAnalyzer version beta 0.87
Spam is going to part of the internet for the foreseeable future, and unmoderated newsgroups are always going to be subject to unwanted intrusions. I suggest you learn to use killfiles and ignore...
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15 years ago
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Change clock domain for FIFO ...
Hi, I have to introduce a DVB Trasnport Stream (Clk + Data + Sync) from a tuner in a fpga. Fpga has a 27 MHz clock with which takes data from the tuner and serializes them to ASI. The serialization...
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15 years ago
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instantiation in verilog
hi i dont know how to make a top module and create instances of other modules in it. my top module is CHK and other modules are BUFFER1, BUFFER2 and BUFFER3. now i want to create their instances in my...
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15 years ago
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Xilinx EDK OPB bus compatibility
Hi, I'm new in FPGA design and I have a question about Xilinx EDK. There are different versions of the OPB bus. Some cores use newest versions but others use older versions. So how can I use different...
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15 years ago
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Howto disable Quartus infering M4Ks??
I have some problems with a design I am porting from Xilinx to Altera. The fitter dies with a message about the design not fitting into the device.Further investiogation shows that Quartus tries to...
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15 years ago
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