Field-Programmable Gate Arrays

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Synplify compile points keep getting resynthesized

Hi all, For some reason synplify is resynthesizing my compile points even though the compile points' rtl have not chang...
0 comments posted 15yrs
posted by anonymous.reply.sender
0 comments posted 15yrs posted by anonymous.reply.sender

question about vtr

dear all, I want to run scripts in "vtr_relase/reg_test/script". but I could not run them, I don not know how I can pass...
0 comments posted 15yrs
posted by sahar.mousavi
0 comments posted 15yrs posted by sahar.mousavi

Xcell Journal issue 75 now available

We've now published the spring 2011 edition of Xcell Journal (issue 75), which a cover story on Xilinx's new Zynq-7000...
0 comments posted 15yrs
posted by mike.santarini
0 comments posted 15yrs posted by mike.santarini

Re: Xilinx ML605 Demo Qusstion

> > > > > > > Ed McGettigan wrote: > > > > Did you buy the EK-V6-ML605-G (base) or the DK-V6-EMBD-G-XP1 (embedde= d > >...
0 comments posted 15yrs
posted by ed.mcgettigan
0 comments posted 15yrs posted by ed.mcgettigan

Re: Ralph Lauren polo

freelance writer
0 comments posted 15yrs
posted by user
0 comments posted 15yrs posted by user

why holdtime is not considerd for Tclkmax calculation

Hi ALL, i just wanted to know why hold time is not considered when we are calculating the Max Frequncy of the sequentia...
0 comments posted 18yrs
posted by ekavirsrikanth
0 comments posted 18yrs posted by ekavirsrikanth

DVI to BT.656

Hi All, Has anyone tried to convert DVI format to BT.656? Is there any IP or Reference design available for this? Regard...
0 comments posted 18yrs
posted by mailtoakshat
0 comments posted 18yrs posted by mailtoakshat

Re: ANNOUNCE: TimingAnalyzer version beta 0.87

>I'm not trying to bust anyone's balls. But this guy has been >cluttering up a number of newsgroups, Yahoo groups and w...
5 comments posted 18yrs
posted by eric.jacobsen
5 comments posted 18yrs posted by eric.jacobsen

Change clock domain for FIFO ...

Hi, I have to introduce a DVB Trasnport Stream (Clk + Data + Sync) from a tuner in a fpga. Fpga has a 27 MHz clock with...
11 comments posted 18yrs
posted by 78kappa78(at)virgilio(dot)it
11 comments posted 18yrs posted by 78kappa78(at)virgilio(dot)it

instantiation in verilog

hi i dont know how to make a top module and create instances of other modules in it. my top module is CHK and other mod...
1 comments posted 18yrs
posted by amboafridi
1 comments posted 18yrs posted by amboafridi

Xilinx EDK OPB bus compatibility

Hi, I'm new in FPGA design and I have a question about Xilinx EDK. There are different versions of the OPB bus. Some co...
0 comments posted 18yrs
posted by a80x86
0 comments posted 18yrs posted by a80x86

Howto disable Quartus infering M4Ks??

I have some problems with a design I am porting from Xilinx to Altera. The fitter dies with a message about the design...
4 comments posted 18yrs
posted by tgau3qk4
4 comments posted 18yrs posted by tgau3qk4

The littlest CPU

I may need to add a CPU to a design I am doing. I had rolled my own core once with a 16 bit data path and it worked out...
12 comments posted 18yrs
posted by gnuarm
12 comments posted 18yrs posted by gnuarm