Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Chipscope with Spartan 3E Starter Kit
Hi, I have a project based on MicroBlaze. Everything works fine, I debug software in SDK. But now I need to check in/out signals and transmission between IPs. So I add Chipscope ICON and ILA (I also...
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17 years ago
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Need help to buy first FPGA board!
Hi everyone, I am newbie in FPGA; recently I decide to buy a FPGA board to study. I am considering two boards: 1. Virtex-4 MB (DS-KIT-4VLX60MB) with XC4VLX60 Virtex-4 ML405 Embedded Platform...
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17 years ago
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Need heep to buy first FPGA board!
Hi everyone, I am newbie in FPGA; recently I decide to buy a FPGA board to study. I am considering two boards: 1. Virtex-4 MB (DS-KIT-4VLX60MB) with XC4VLX60 Virtex-4 ML405 Embedded Platform...
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17 years ago
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Structured ASIC players
NEC will exit the structured ASIC business Is that 2 major players gone? How many more are there? - John_H
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17 years ago
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internal DCM
Hi Can any body explain internal DCM and give me some information about it? Thank you
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17 years ago
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2x technique
Hi Is there a technique to 2x our input clock and as a general Is there a technique to create a clock with frequency of n*f_input_clk. (where n is a desired integer) Thank you
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17 years ago
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MicroBlaze and OPB block ram interface controller run at different frequency
Hello, all: My question is: Can MicroBlaze and OPB run at one clock frequency and the OPB block ram interface run at another? If it is possible, how can I relize it? Can I change the BRAM_clk someway?...
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17 years ago
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porting virtex2-pro into virtex4. Performance!!
Hello. I implemented floating point adder in virtex2-pro and now recomplied it in virtex4. There is no compile error in synthsis & implement. But the performance (speed) is a little reduced. So I want...
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17 years ago
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VHDL code for Generating registers
I want to generate a program in VHDL for generating registers which can be used then into a state machine. If anyone has a sample program to share, it will be very helpful. Thanks and regards, sandip
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17 years ago
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Using Xilinx DCM FX output without DLL
I need to design an FPGA for a chip bringup system with the following clocking requirements: There is a 2.75 MHz input clock from the DUT. One part of the FPGA-DUT interface is running on this clock....
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17 years ago
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Determine error in asynchronous signal
Hi, first of all, I know that asynchronous signals are bad, etc but that's what i have to work with. I am using Spartan 3E FPGA. I have an internal clock running at 125 MHz. I cannot use any DCM for...
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17 years ago
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Can someone give me some pointers on using ibis models?
Hi, I have been doing designs, digital and analog, for over 20 years, without making use of ibis data, but I think that is about to end. I was doing a design with one of the newer Altera BGA's and...
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17 years ago
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OPB IPIF: write to DIER causing bus timeout
I'm talking to an IPIF device on the OPB bus from a linux driver. My problem is that when I try to write to the DIER register to enable device interrupts, linux gives me a bus error. (Enabling,...
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17 years ago
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how to use STD_LOGIC_VECTOR2
Hi I need to convert type : array (0 to 3) of std_logic_vector (31 downto 0) to type : STD_LOGIC_VECTOR2 ( 3 downto 0 , 31 downto 0 ) As an example, I was using signal DATA_TEMP(3)
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17 years ago
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up down lfsr
how to create an 8 bit up down lfsr
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17 years ago
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