Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Digital AM/FM Receiver - Systemic Question
Hi There! I did start a post earlier with the title " Digital AM/FM Receiver", and I'm starting one again in continuation to that (the reason for starting another post is selfish....get more...
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17 years ago
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Looking for resources on timing analysis
I have been doing FPGA design work for a few years now and must admit that timing analysis scares me because it is something I didn't learn in school. We use Xilinx FPGA's at the company where I...
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17 years ago
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Manual LUT - AND function mapping problem
Dear all I am trying to manually map "2-bit AND" function into single slice, with no luck -: I type the commands below in the FPGA editor. Problem is that, "F" port of slice is NOT connected to "D"...
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17 years ago
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how to shift mutiple bytes in an array in one clock cycle?
i have a byte array of size 10 and i need to shift values in the array to left by 5 positions in 5 clocks. here is the code im using. reg [7:0] data[0:9]; // data shifting process reg ps_shift_start;...
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17 years ago
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gated clock
hi, I have a design with two clock that I want to mux toward a single clock like this with mode select CLK
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17 years ago
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LZW compression and decompression in vhdl
Hi, can somebody help me to find an implementation of LZW compression/decompression algorithm in VHDL? Thanks a lot. Eric
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17 years ago
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CPLD erase??
Working with a coolrunner2 CPLD. Is there a way to erase whatever has been programmed into the CPLD, without using JTAG?
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17 years ago
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How to generate STAPL with "pulse PROG" in Impact?
Hi All, I'm using the STAPL player to configure my Xilinx chips via JTAG interface. However to get them running correctly, I have to generate the "PROG pulse" (as it was often discussed in this...
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17 years ago
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Data width in Block ram
I have to generate a block ram in xilinx. The data width is not fixed and it will be changed according to the requirement of project. I have noticed that the data width in the block ram has been...
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17 years ago
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How to make use of two processors with Xilinx ISE (on Linux)
When I did this on several years ago on our multi-cpu SUN's I just listed the hostname multiple times using a mix of upper and lower case letters , e.g. xlx xLx xLX Xlx would run four processes on the...
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17 years ago
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Austin the Altera Mole
Is he? First Austin admits Cyclone 3 is lower power than S3E or V5. Then he tells us to stop using XST for real designs. All in one day. Please, someone from Altera send him a fruit basket. Ricky...
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17 years ago
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how to make a matlab simulink wave into mif or hex form.
i use matlab simulink to produce a wave .I want to make the wave in the .mif or .hex form .so i can load the wave to ROM.how to make a wave into mif or hex
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17 years ago
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Why is Xilinx's WebPACK so inferior?
I've been using the Xilinx Webpack 8.2i since sometime in November, and I've become so irritated with their software that I'm about ready to just become a rabid Xilinx basher. I've encountered...
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17 years ago
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Virtex-II block RAM problem
Hello, I am running into a strange problem with the dual-port block RAM in Virtex-II and at this point have run out of ideas :( In my design I am trying to perform data acquisition on a 32-bit...
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17 years ago
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Zero-Valued Data Out of Chipscope ILA?
Hello, I have a design on a SX55 that contains of two complex (real +imaginary) datapaths. I've been trying to debug the code in Chipscope using ILAs before and after my processing block. Both...
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17 years ago
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