I have been doing FPGA design work for a few years now and must admit that timing analysis scares me because it is something I didn't learn in school. We use Xilinx FPGA's at the company where I currently work, and I am somewhat familiar with the ISE Timing Analyzer tool. However, I am looking to learn how to do timing analysis manually before using the tool, because I feel it is becoming more and more important as bus speeds are increasing, not to mention it's a good skill to add to a resume. Can anyone suggest any resources, whether they be online or perhaps a good book? I'm looking to have an understanding of the various parameters one must take into account when analyzing timing budgets for both system and source synchronous interfaces, including board-level effects. Any information would greatly be appreciated.
Looking for resources on timing analysis
Mar 21, 2007
4 Replies
Hi,
Go here:
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and check Lecture Module 3. This is only an introduction for synchronous digital circuits with a single clock. It only gets more complicated from there...
Eric
Thanks for the link! I think I'm mainly looking to be at a point where I would feel comfortable doing some initial timing analysis on an FPGA I/O interface such as SPI-4 or DDR2, or perhaps something system synchronous. Do you know of any detailed examples of where this might be done so I can get a feel for it? I'll leave most of the internal analysis to the software tools I think. =)
I don't know of a comprehensive resource exists (if someone else does, please share!)
There are some Xilinx application notes that discuss it; most are very specific to a particular interface. This is the most general I could find:
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I also stumbled across this, which I found interesting reading:
download.intel.com/education/highered/signal/ELCT762/Class03_Signal_Parameters_II.ppt
Eric
find:
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download.intel.com/education/highered/signal/ELCT762/Class03_Signal_Parameters_II.ppt
Maybe this helps
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