Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Generating video noise.
I want to program an FPGA to generate two-dimensional, 10-bit video white noise. Any suggestions? I'm not sure if an independent LFSR per bit would work. If so, would I want different lengths per bit,...
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16 years ago
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8B/10B decoding after serial transmission problem?
Hello, I run into a problem/bug where I currently don't see a solution, probably somebody can give me some hints. I encoded data frames with 8B/10B, filled the gaps between the data with K28.5...
2
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16 years ago
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Actel. Libero. Synplify
when I synthesize the FPGA (ProASIC PLUS) in Synplify of Libero I have got a lot of warnings: "Unbound component (DFF or AND2...) mapped to black box". It seems that don't recognize the basic...
3
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16 years ago
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XC9572XL bus hold - Cant be disabled
No matter what options I use, the bus hold circuits are enabled on the inputs of a XC9572XL (same problem with 95144XL) in a design of ours. I've tried ISE6.3 and WEBPack 9.1, no difference. The...
2
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16 years ago
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BD
Hai, I need to know how to generate buffer descriptor file? regards, fazal
5
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16 years ago
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Sending large amount of data with lwIP...
Hello, I'm trying to send an image with lwIP, the problem is that I can't XD, y read the image from the CF card, so suposse it takes 10000 bytes, but my sendbuf is only 8192, how can I send data...
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16 years ago
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Unisim versus Virtex2 Xilinx Library
Hi, I have seen a piece of code in which there is elements such as FDP, BUFG and DCM. This code is to get different clocks from internal reference clock. I have simulated this but I cannot. These...
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16 years ago
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Xilinx S3 Starterkit, how hot it is supposed to be?
Hi I just burnt my fingers trying to lift off the Xilinx Spartan 3A Starterkit the all corner with power supplies is extremly hot - I wonder if that is normal or not. I already own 3 FPGA boards...
15
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16 years ago
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15 | |
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Req: (Free) Embedded Platforms for Education
Hi all, First of all I just joined this group so let me salute all members !! I have a request and I would be happy is someone could help. You all probably know that embedded systems are more and more...
5
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16 years ago
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5 | |
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Xilinx XC9536 current draw ?
Hello, I have been trying to figure out why the current draw of an XC9536 (not -XL) chip is so high. Xilinx has been of some help, but can't explain why the current I'm seeing (now 70 - 95 mA) is...
15
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16 years ago
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Xilinx System generator vs Simulink HDL Coder
Hi all, Anyone know the differences between Xilinx System Generator and Simulink HDL Coder? Thanks a lot. Richie
2
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16 years ago
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chipscope PLB IBA - how to get meaningful labels on signals?
I have been trying chipscope from within XPS 9.1.03i on a ML403. I can connect up the ILA sucessfully and can capture and display signals. I can also instantiate and build and run the PLB IBA core....
4
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16 years ago
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EDK9.1 LWIP network stack crashing?
Greetings all, I'm encountering a problem with the lwip network stack. Perhaps someone can spot what I'm missing. My hardware is an ML405 board. I'm using essentially the reference PPC design with the...
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16 years ago
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How to obtain (accurate) critical path delay?
Dear Asking many questions on this board --: My goal is to get "critical path delay" (or maximum clock frequency) of simple "register file", as described in the following : ---------------------------...
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16 years ago
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1ms delay in V5 FPGA
I need to generate approximately 1ms delay in Virtex5 -3 FPGA. The fabric clock is running at 200MHz. I was thinking about using 20 bit timer to achieve this as the wait is fairly integarted in the...
4
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16 years ago
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