Field-Programmable Gate Arrays

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Actel. Libero. Synplify

when I synthesize the FPGA (ProASIC PLUS) in Synplify of Libero I have got a lot of warnings: "Unbound component (DFF o...
3 comments posted 19yrs
posted by dorama2
3 comments posted 19yrs posted by dorama2

XC9572XL bus hold - Cant be disabled

No matter what options I use, the bus hold circuits are enabled on the inputs of a XC9572XL (same problem with 95144XL)...
2 comments posted 19yrs
posted by pcw
2 comments posted 19yrs posted by pcw

BD

Hai, I need to know how to generate buffer descriptor file? regards, fazal
5 comments posted 19yrs
posted by fazulu.vlsi
5 comments posted 19yrs posted by fazulu.vlsi

Sending large amount of data with lwIP...

Hello, I'm trying to send an image with lwIP, the problem is that I can't XD, y read the image from the CF card, so sup...
0 comments posted 19yrs
posted by periket2000
0 comments posted 19yrs posted by periket2000

Unisim versus Virtex2 Xilinx Library

Hi, I have seen a piece of code in which there is elements such as FDP, BUFG and DCM. This code is to get different clo...
0 comments posted 19yrs
posted by pbantunez
0 comments posted 19yrs posted by pbantunez

Xilinx S3 Starterkit, how hot it is supposed to be?

Hi I just burnt my fingers trying to lift off the Xilinx Spartan 3A Starterkit the all corner with power supplies is ex...
15 comments posted 19yrs
posted by Antti.Lukats
15 comments posted 19yrs posted by Antti.Lukats

Req: (Free) Embedded Platforms for Education

Hi all, First of all I just joined this group so let me salute all members !! I have a request and I would be happy is...
5 comments posted 19yrs
posted by gouaich
5 comments posted 19yrs posted by gouaich

Xilinx XC9536 current draw ?

Hello, I have been trying to figure out why the current draw of an XC9536 (not -XL) chip is so high. Xilinx has been of...
15 comments posted 19yrs
posted by elson
15 comments posted 19yrs posted by elson

Xilinx System generator vs Simulink HDL Coder

Hi all, Anyone know the differences between Xilinx System Generator and Simulink HDL Coder? Thanks a lot. Richie
2 comments posted 19yrs
posted by richng01
2 comments posted 19yrs posted by richng01

EDK9.1 LWIP network stack crashing?

Greetings all, I'm encountering a problem with the lwip network stack. Perhaps someone can spot what I'm missing. My ha...
0 comments posted 19yrs
posted by newsryan
0 comments posted 19yrs posted by newsryan

How to obtain (accurate) critical path delay?

Dear Asking many questions on this board --: My goal is to get "critical path delay" (or maximum clock frequency) of si...
0 comments posted 19yrs
posted by pasacco
0 comments posted 19yrs posted by pasacco

1ms delay in V5 FPGA

I need to generate approximately 1ms delay in Virtex5 -3 FPGA. The fabric clock is running at 200MHz. I was thinking ab...
4 comments posted 19yrs
posted by
4 comments posted 19yrs posted by

Timing in Modelsim

Hello, I'm trying to simulate my design in modelsim and i'm trying to find out if it is possible to choose the set_up d...
3 comments posted 19yrs
posted by roche.alexis
3 comments posted 19yrs posted by roche.alexis