Latest threads in Field-Programmable Gate Arrays

On I2C protocol

As for the I2C Master, assuming no clock stretching is issued by the Slave, here is a common situation and its concerni...

15 19yrs

me

15 19yrs me

help: buggy IDE driver on Intel IXP425 GPIO(EXPB)

I have to use this ide vhdl driver that's supposed to link an IDE channel to the expansion bus of an IXP425 Intel proce...

0 19yrs

metiu.uitem

0 19yrs metiu.uitem

xilinx multichannel fir alignment

I'm using the v5.1 coregen fir, decimate by 2, two channel operation to process my I/Q. My system clock is 56 Mhz and t...

3 19yrs

cepope

3 19yrs cepope

Could you explain the procedure about system simulation?

Hi I'm studying Embedded system using XUPVP2PRO and use the tools ISE 8.1, EDK 8.1 and ModelSim 6.0 SE. I want to verif...

0 19yrs

SangchulJung

0 19yrs SangchulJung

FIFO Full logix - V4

I am working with a dual port RAM FIFO module that has a 32-bit write port and an 8-bit read port using asynchronous cl...

2 19yrs

mottoblatto

2 19yrs mottoblatto

FPGA for HPC

Dear, I'd like to learn programming FPGAs for HPC applications. I am, however, a newbie in this field. I do have a soft...

1 19yrs

bart.deboeck

1 19yrs bart.deboeck

watchdog timer: interrupt handler: microblaze

I have been trying to write a watchdog interrupt handler and have not been successful in coming up with a working code....

1 19yrs

azizul.islam

1 19yrs azizul.islam

FIFO : Synchronous WRITE, Asynchronous READ ?

Dear Using BRAM (for example, RAMB16_S36_S36), I do need to implement "synchronous WRITE, asynchronous READ" FIFO. >Fro...

3 19yrs

pasacco

3 19yrs pasacco

how do Xilinx PCSPMA IP core detect presence of optical input?

I use Xilinx PCSPMA GTP IP core to connect SFP interface. But how to connect the signal_detect signal of PCSPMA GTP core...

0 19yrs

water9580

0 19yrs water9580

Running Virtex5 GTP at lower data rate

At power-up, I need to run the Virtex GTP at 400Mbps and then after the initialization, I need to run the V5 GTP at 3.2...

4 19yrs

Writing to bram and reading from bram with microblazer

Hello, I am a newbie in microblaze.I'm trying to implement a basic data readin and writing to bram with microblaze.Can...

3 19yrs

mfgunes

3 19yrs mfgunes

Xilinx fpgas...

I've been looking at the Spartan 3an's mostly, because of the built-in config flash, but I've yet to settle on them as...

7 19yrs

john.m.oyler

7 19yrs john.m.oyler

libero.actel. i need a clock in a non global pin.

Is possible force the assignation of a clock to a pin (non global pin)? (=BFcan i do before synthesize?) On synthesis t...

1 19yrs

dorama2

1 19yrs dorama2

SDRAM vs DDR2 on Spartan3E

Hi all, I am considering to replace a SDRAM with a DDR2 on a custom Spartan3E1200 board to gain some bandwidth in a Mic...

1 19yrs

ales.gorkic

1 19yrs ales.gorkic

DDR2 vs SDR on Spartan3

Hi to all, I am considering to replace the x16 SDRAM for a x16 DDR2 to gain some bandwidth for a MicroBlaze system. I w...

3 19yrs

ales.gorkic

3 19yrs ales.gorkic

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