I need to generate approximately 1ms delay in Virtex5 -3 FPGA. The fabric clock is running at 200MHz. I was thinking about using 20 bit timer to achieve this as the wait is fairly integarted in the state machine so having a simple counter makes it easy. I basically look for a specific count value in a particular state if not I keep incrementing the count.
Is this the right way to achieve the delays?
Thanks.
Wei
It might be easier to only allow state transitions when the counter is at a specific value. This will make your state machine more understandable and easier to maintain.
---Matthew Hicks
clock is running at 200MHz. I was thinking about using 20 bit timer t achieve this as the wait is fairly integarted in the state machine s having a simple counter makes it easy. I basically look for a specifi count value in a particular state if not I keep incrementing the count.
That should work. Make sure you clear the counter on entry to the waitin state. It is good practice to exit on "greater than or equal to" rathe than "equal to" despite the former using slightly more combinatorial logi resources.
That sounds reasonable. Don't forget to reset the counter before entering the state where you delay. Also, you might not need to compare all 20 bits. For instance if you can pick your wait time to be 2**N clocks you can say "if counter(16) = '1'" instead of "if counter =
65536" which will be smaller and faster.-Jeff
Better yet, set the count to whatever period you need immediately prior to entering the waiting state, and wait for it to go to zero by checking the carry bit out of the decrementer (down counter).
Andy
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