I need to generate approximately 1ms delay in Virtex5 -3 FPGA. The fabric clock is running at 200MHz. I was thinking about using 20 bit timer to achieve this as the wait is fairly integarted in the state machine so having a simple counter makes it easy. I basically look for a specific count value in a particular state if not I keep incrementing the count.
Is this the right way to achieve the delays?
Thanks.
Wei