Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
ICAP in Virtex 4
Hello, Has anyone succeeded to do module based, dynamic partial reconfiguration in a Virtex4 Device with the ICAP? I am trying to load a Partial Bitstream with the OPB_HWICAP peripheral included in...
—
|
16 years ago
|
— | |
|
|
Xilinx, converting ncd back to edif
Hello everyone, I have a placed and routed .ncd file and I'd like to be able to convert it back to a simple netlist. It doesn't contain any "secured" core, so I can freely use all the xilinx tools...
6
|
16 years ago
|
6 | |
|
|
XMD crashes on EDK 9.1i
Hello Group Members I am trying to build a simple system consisting of PowerPC405, JTAG, UART, OPB DDR controller, and 16MB External DDR memory on a HiTech PPC board. No on-chip BRAMs. I use EDK...
1
|
16 years ago
|
1 | |
|
|
Question about Bottom-Up Incremental Compilation Methodology in Quartus II
I am new to use Bottom-Up Incremental Compilation Methodology in Quartus and I have a question about it. I have exported partition from subproject and imported it to top-level design successfully....
7
|
16 years ago
|
7 | |
|
|
Why is Xilinx XPS 8.2i so slow?
Gang I created a half dozen example projects using ISE 8.2i and the PicoBlaze on my S3-1600 Dev Board. I'm really comfortable with asm programming so the lack of a C compiler was no big deal. I am...
2
|
16 years ago
|
2 | |
|
|
Timing simulation
I would like to know how to have easy access to the internal state machines and registers in its ennitrity while doing the timing simulation. The timing simulation verilog output generated by the...
7
|
16 years ago
|
7 | |
|
|
Xilinx VHDL multidimensional array synthesis
Hello, I was working on a video font which I initially did as a 2 dimensional array of std_logic_vectors, one dimension for the bit output, and the other for the character and row selection. I suppose...
5
|
16 years ago
|
5 | |
|
|
EDK Microblaze project without OPB?
Hi, all. Is it known to be possible to create a Microblaze system without the OPB? For example, say I have 1 MicroBlaze with 16KB of d&i BRAM, but I don't necessarily need the off-chip SDRAM or UART...
2
|
16 years ago
|
2 | |
|
|
Anyone know any good vhdl ethernet tutorials?
I don't know that my fpga is capable (spartan 3e 100k), but I thought I might like to try to do ethernet first. I remember finding a tutorial weeks ago but forgot to bookmark it, where the...
2
|
16 years ago
|
2 | |
|
|
Virtex-5 and powerpc
I cannot find any reference to powerPC cores in any of the Virtex-5 datasheets. The only reference to PowerPC in those documents is that PowerPC is a trademark of IBM. Does anyone know if Xilinx...
6
|
16 years ago
|
6 | |
|
|
PC104+ communication with FPGA using Xilinx IPCore
Hi, I was wondering if anyone has ever use FPGA to communicate with another board that use PC/104 plus bus as the interface? To give a better view, I have one firewire board that uses a PCI-to-1394...
3
|
16 years ago
|
3 | |
|
|
ERROR:NgdBuild:927 - Failed to process BMM file edkBmmFile.bmm
Hello, I am trying to import xmp file to my ise project.But i facing with thi error on you help me to solve this problem?
4
|
16 years ago
|
4 | |
|
|
Beginners question
Dear Group, I have a xilinx xc9536 , a 22 bit counter, and a 5 bit counter. The 22 bit counter is used as a 48mhz clock divider for the other 5 bit counter, hence bit 22 is used as humanly visible...
16
|
16 years ago
|
16 | |
|
|
verilog parser question about `defines
I have a set of verilog files that uses `defines. The same `define is applied to each file to select which code to use. Is there a way to setup Xilinx ISE so that when processing all verilog files it...
3
|
16 years ago
|
3 | |
|
|
pci express pinout
Would anyone here know the history of pin B3 on the pci express connector? The latest PCISIG document shows it as +12V with no change bar associated with it. However I have found reference designs...
3
|
16 years ago
|
3 |