Xilinx, converting ncd back to edif

You can convert it to a verilog netlist with netgen, here's from one of my older Makefiles:

netgen -sim -aka -dir . -ofmt verilog -pcf $(CHIP).pcf -sdf_anno true -sdf_path ../../impl/2vp20/xst-compiled -w $< $@

Petter

back to a simple netlist.

tools suite on it. But there is no "ncd2edif" ...

configuration, which means I would have to convert it to a basic element (LUT/MUXF5/...) + interconnections first ... That's gonna be quite painful to do.

Presumably you have the NGD which you used to create the NCD. Then you can use NDG2EDIF.

No I don't ;)

All I have recovered is the .ncd, the .bit, and all the .ngc except one ... I'm hoping to be able to reconstruct my missing ngc by "isolating" it from the rest in the ngc.

I tried netgen, that gives me a vhdl (or verilog file), but parsing it is gonna be painful as well ;)

Sylvain

-sdf_path ../../impl/2vp20/xst-compiled -w $< $@

Thanks, that's a start.

Maybe by running xst on it I'll get an edif ...

Sylvain

If you use netgen with an .ncd netlist, you can only retrieve a post-mapped netlist, which is not synthesizable and usually does not contain any hierarchy any more. Also, it contains additional symbols for buffers and routing path delay.

If you discover a method to translate the .xdl primitives (slices, iobs) back into an .edf let us know!

-Markus

It's not entirely true that netgen HDL can't be resynthesized. I've done that often in order to use Synplify's schematic viewer to view an NGC created by XST. Well, I guess I've run netgen postsynthesis, which is a bit different than running it post-PAR, because the former uses UNISIMs and the latter SIMPRIMs, and maybe the SIMPRIMs aren't as synthesizable. Of course it would be possible to make your own synthesizable SIMPRIM library, but that's a ton of work, and anyway, by the time you get a new netlist from the ncd your names are going to be so munged it won't make much sense. -Kevin