Hi ,
I am new programmer in VHDL and i have to realize a DLL in an ACTEL ProASIC board.
I am using Libero 4.6 and Model Sim 5.6b.
I have decided to use as example the 74HC297.
I am having problems to implement a Edge Controlled phase detector using a simple SRlatch!(not a doubble SRlatch!)
CAn anyone tell me why I got this message on ModelSim: "Iteration limit reached. Possible zero delay oscillation. See the manual."
Is not possible to instatiate a simple Latch on Fpga?
I am sure to instante a latch because I have veruified on the netlist in Synplify! and on the Designer netlist a Dlatch has been implemented!
Is it only a problem in the use of a Simulator?
Furthermore I am trying to simulate a simple Dlatch with asyncronous clear with the following testbench:
1) D imput line a signal that represent the frequency I want to lock. 2) Clear input a signal that is opposite to D that represent the frequency that come from the DCO(to "simulate" a phase detector in the case when I am in Lock state )Thanks for any help! and tips you can suggest!
Massimo