clocks switch

Hi Dan,

You can use an assignment statement to create a input mux to switch your clocks. Something like this should do the trick:

module mux3 (clk1, clk2, clk3, select, clkout);

input clk1, clk2, clk3; input [1:0]select; output clkout;

wire clkout;

assign clkout = select == 2'b00 ? clk1 : select == 2'b01 ? clk2 : clk3; //

endmodule

Then all you need to do is to make a counter that's based on the selected clkout to change your switch signal.

Just something like always @(posedge clkout) counter I need to make first 200 pulses of CLK with clk1, then 600 pulses of

Hi Dan,

You need to draw wave forms of the 3 clocks and their individual select signals to make sure that they will not generate glitches at the transition time. (Think of a circuit when the select signal goes low and clock edge goes high at the same time, will an unwanted glitch be generated?)

If the clocks are totally independent with each other, you need to use double-FFs to synchronize between async boundary for each transition to eliminate meta-stable possibilities. The circuit is a lot more complex than the circuit below.

It is a little simpler (but you still need to check the waveforms thoroughly) if the 3 clocks are generated from the same source.

The counter should be simple to implement.

Ch>Matthew Plante wrote: