bufgmux

Keith,

The tools will use local interconnect to find an entry to the BUFG tree (you will also geta warning).

This means that you will have an unknown skew, and added possibility for jitter.

Depends on what you are doing, but if you care about delay, or phase, don't do it.

Aust> I had a rather silly question, but the documentation has been rather

confusing. If my understanding is correct, i can send clock signals on normal IO pins (not gclk pins) and then define a bufgmux in my VHDL code and it will globally route it. Is my understanding correct? I don't have to route my two clocks to clk pins and THEN put a BUFGMUX do i?

Ok. So if i were to route the two clocks onto clock pins, and then use a bufgmux, would this eliminate that problem?

Thanks,

Keith

Keith,

"that problem" depends on if you care about phase or delay.

But yes, if you use the global clock input pins, they have dedicated routes to the BUFG(MUX)s that are characterized and understood by the software.

Aust> Ok. So if i were to route the two clocks onto clock pins, and then use a

bufgmux, would this eliminate that problem?