VIRTEXII IO problem

Nov 13, 2003 0 Replies

Hey, i have this problem when i want to do the following thing:



I have this serial input (let's call it a) and i want to see the serial input a through an IO provided on my evaluation board (let's call that pin atest) and i did it like this



entity testmodule is port( a, clk: in std_logic; b, atest: out std_logic ); end testmodule;



architecture Behavioral of testmodule is



begin


-- the rest of the program to get a =>b


--with this process i want to feed the input a to and debug output atest which it clocked on the clk (which is a lot



--faster than the serial clock so there should be no problem there process(clk) begin if (clk'event and clk='1') then atest


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