Does such a chip exist? I can't find it.
MAX9375 or PTN3310 = Single LVDS to LVPECL tb5d1m = Quad LVTTL to LVPECL MC10H352-D = Quad CMOS to PECL sn65lvelt22 = Dual LVTTL to LVPECL MC100EPT622-D (obsolete) = 10-bit LVTTL to single-ended LVPECL and I only want single-ended LVPECL to drive 4 data inputs on a MC100EP142
Any suggestions?
TIA
See page 3...
Looks like all it takes is an R-network.
Also see page 3...
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
The only thing bipartisan in this country is hypocrisy
You could use something like a 10EP17, a quad ecl diff-in, diff-out buffer. Its inputs are (probably...check me on this) LVDS compatible, and its outputs are ECL.
If your LVDS common-mode voltage is too low to meet the common-mode input specs of the EP17, you can power it from +3.3 and -2 or something like that. It's good to 5.5 volts.
John
OnSemi do a MC100LVEL17 which is 3V3 PECL levels.
Their PECL data sheets show internal input pull downs to VEE and talk about inputs having default states if left open. This sounds like it's OK for the input to go all the way down to VEE; but then the DC characteristics give min/max VIH/VIL that are strictly PECL spec. They also have an app note AN1503-D which gives Spice info including input / output internal schematics which look like they'd be totally screwed by rail-to-rail inputs.
Just because an input is _allowed_ to go all the way to VEE doesn't mean it will necessarily produce a legitimate output.
Since what I've previously posted showed resistive level shifting I doubt that you can directly make a connection from LVDS-out to PECL-in.
Study what I've posted AND the LVDS and PECL data sheets. ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
The only thing bipartisan in this country is hypocrisy
The EP input is just an NPN differential pair. The min/max specs are for single-ended inputs working against Vbb, which isn't what I suggest. LVDS is differential and doesn't go rail-to-rail.
Assuming a 3.3 volt supply:
The LVDS common-mode voltage will be around +1.2 and the lines will wiggle a couple of hundred millivolts. The minimum common-mode voltage on the EP17 is spec'd as VEE+2, which is +2 if you run the EP from
+3.3 and ground. So direct LVDS drive is out of spec.But if you run the EP from +3.3 and -2, then the input common-mode extends down to VEE+2, namely ground. Then it should be happy with direct LVDS diferential inputs.
The EP17 outputs will still be ECL referenced to +3.3, namely PECL.
John
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