V5 LVPECL Inputs

1100mv. Thus each arm of the differential signal has 550 mV swing and Vcm being Vcc - 0.275V (3.3 - 0.275 = 3.025V). 2.2V. This does not match with the Non Xiilnx output driver with Vcm = 3.025V

You claim that the output voltage , at its most positive, is 275 mV more positive than its Vcc. Can that be true? Peter Alfke, from home

1100mv. Thus each arm of the differential signal has 550 mV swing and Vcm being Vcc - 0.275V (3.3 - 0.275 = 3.025V). 2.2V. This does not match with the Non Xiilnx output driver with Vcm = 3.025V

Your non-Xilinx drivers aren't LVPECL, are they? What is your driver? Does its common-mode range have to be so high?

The output voltage at its most positve will be Vcc, the Vcm will be Vcc - 0.275 and the low voltage will be Vcc - 0.55 This gives 550 mv swing on each arm and

1100mv differential swing.

This is an Inphi driver which supports PCML standard.

Here is a text directly from Inphi application note:

"The HSL outputs are VCC referenced. This means that if an output has a typical

1100 mVp-p differential swing (i.e. 550 mVp-p on each arm), then each output (primary and complementary) varies between approximately Vcc and Vcc - 0.55V, which suggests a common mode voltage, Vcm, that is the average of that range (i.e. Vcc - 0.275V)."

The non-Xilinx driver is not LVPECL. It is CML driver from Inphi.

A "differential voltage" of 1100 mv implies that each leg is Vcm +/-

550 mv. If Vcm = Vcc - 0.275, then the high leg is in fact above Vcc for the driver.

One or more parts of your original specification are likely not correct.

Andy

Andy,

It will be great if you can elaborate.

Andy,

Here is what I have from the datsheet.

The HSL outputs are VCC referenced. This means that if an output has a typical

1100 mVp-p differential swing (i.e. 550 mVp-p on each arm), then each output (primary and complementary) varies between approximately Vcc and Vcc - 0.55V, which suggests a common mode voltage, Vcm, that is the average of that range (i.e. Vcc - 0.275V)."

1100 mVp-p differential swing (i.e. 550 mVp-p on each arm), then each output (primary and complementary) varies between approximately Vcc and Vcc - 0.55V, which suggests a common mode voltage, Vcm, that is the average of that range (i.e. Vcc - 0.275V)."

You're right, my bad. However, just because the output is referenced from Vcc does NOT mean that one end is @ Vcc. I would not assume that Vcm = Vcc - (Vopp/2) just from what you told me.

Andy

Further reading of the data sheet suggested that the part has a separate pin to control the Vcm from 1.8v to 3.3V.

For 1.8V Vcm, the High voltage will be 2.075V and the low voltage will be 1.525V.

Can the Xilinx LVPECL input take this ampitude of Vcm = 1.8V and 1100 mV differential voltage (Vhigh = 2.075V, Vcm = 1.8V and Vlow = 1.525V)?

Thanks.

to control the Vcm from 1.8v to 3.3V.

1.525V.

differential voltage (Vhigh = 2.075V, Vcm = 1.8V and Vlow = 1.525V)?

The Vityex-5 data book (page 35) calls out: Input common mode voltage between 0.6 V and 2.2 V Differential Input voltahe: 0.1 V to 1.5 V

But input max voltage not to exceed Vccaux by more than 200 mV, and input min voltage not to go below minus 500 mV.

So the answer to your question in: YES, it's ok. Peter Alfke

Are you specifically interfacing to the GTPs? These RocketIO ports *are* CML.

I've had trouble coming across the voltage specifics for the interface in the specs (I spend most of my time in Spartan-land) but you might find that your interface is simpler than you imagined. If you're interfacing CML to CML, there's no need to try to support the "niche" LVPECL standard. The IO standards aren't favoring LVPECL across all products anymore.

- John_H

to control the Vcm from 1.8v to 3.3V.

1.525V.

differential voltage (Vhigh = 2.075V, Vcm = 1.8V and Vlow = 1.525V)?

I think this has come up before, and the Diff Comparator is actually rail-rail capable, relative to VccAux - correct ? ISTR it is spec'd for speed over a narrower range, but can operate ok within the rails ? (which is what Peter is saying )

-jg

On the output side, I would like to use Xilinx GTP transceivers. The GTP transceivers will get connected to the LVPECL device with high common mode range of 1.2v to 2.5v and differential swing range of 300mv to 2400mv.

I would like to know the Vhigh, Vlow and Vcm values of GTP transceivers in LVPECL output mode.

As I understand the documantation for the GTPs, there IS no LVPECL "mode" but only CML from the appropriate termination voltage you choose. There should be an acceptable range for the output but I didn't find it in the quick scan of the current data sheet (preliminary information and all that). Perhaps your FAE can get more specifics on the GTP voltage values that have yet to make it into the data sheet tables.

Your input is LVPECL and not CML? I thought you were talking CML in/out in the earlier threads.

We are designing separate transmitter and receiver hardware. We would like to utlize the GTP transceivers for transmitter portion to minimize the complexity. For receiver we do not have a choice but to use the descrete devices in order to run at 3.2 GHz. Our protcol is such that it can not be supported by the GTP transceivers.

Thus for transmitter we would like to use the GTPs and for the receiver we would like to use Select I/Os. It will be separate FPGAs.