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LVPECL and SelectIO banking rules in V2P

Hi *,

I have some doubts on the use of LVPECL25-input buffers. The situation is as follows:

I have a 3.3V-LVPECL-clock source, which I need to connect to a global clock pin that is inside a bank powered with VCCO=3.3V. But the only LVPECL-input buffer available for instantiation in V2P is the IBUFDS_LVPECL_25, hinting at VCCO=2.5V. xapp696 (

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) explains how to connect a 3.3V-LVPECL-Transmitter to a 2.5V-LVPECL-receiver.

But is the IBUFDS_LVPECL_25 really 2.5V, even if it resides in a bank powered with 3.3V? The tools (PACE, map and par) allow to place LVCMOS33 and LVPECL25-IOs in the same bank, so I guess everything should be OK.

Is this because differential input buffers are powered by VCCAUX, which is 2.5V, regardless of the bank's VCCO? Or is an IBUFDS_LVPECL_25 really LVPECL_33 when it's inside a 3.3V-powered bank? In that case I would have to use a different termination scheme...

--
cu,
Sean
Reply to
Sean Durkin
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Hi Sean, Please let me know if you get an answer! Check out these CAF threads where I got some information, but not much. Cheers, Syms.

Differential terminations in Virtex2 Pro. Differential terminations in Virtex2 Pro.Attempt II! Xilinx LVDS_25_DT termination issues????

Reply to
Symon

If driving a Xilinx 2.5V LVPECL input from an external

3.3V LVPECL driver, there's a good chance the driver output swings will exceed the specified Xilinx input common mode range- I'd either AC couple with a bias network (for a continuous clock) or use a resistive level shifter.

Besides XAPP696, see also:

- Answer Record 16830

-

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Yes to both, according to Answer Record 16830. (note, I haven't verified this myself on a V2Pro)

Symon wrote

Check out the recently updated Answer Record 17244 ( no damage, sorta works but lower impedance)

Brian

Reply to
Brian Davis

Thanks Brian! I wonder, is there an email notify thingy when a specific answer record changes? So, as it happens, I know that _DT works on 3.3 Vcco banks to some extent because I tried it on a prototype. I bottled out on the real thing and put a level shifter in for the single ended signals and made it a 2.5 Vcco bank. It still begs the question as to why Xilinx were able to power the differential input from Vccaux, but not the differential termination gizmo. If only they were perfect like what I am. ;-) Thanks again, Syms.

Reply to
Symon

Thanks a bundle for this. Really handy to have it all in one document. And thanks for clearing up some of my doubts. :)

cu, Sean

Reply to
Sean Durkin

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