how to delay a signal in virtex FPGA

you should not do what you are trying todo, but if needed you can one possibility is to make hard-macros and use them there are tricks also possible. but as said, those methods should not be used as the results are hard to keep constant over implementation runs (unless full hardmacro and dedicated routing, and even then)

Antti

Michel Talon posted:

"I've to delay a signal without using clock. [..]"

Would something like intermediary_storage_of_delayed_signal

Hi,

I think you need to add more information around your question in order to be able to give you a better answer.

Delaying something without a clock for a long time (> few ns) is hard since you don't have any control whatsoever on the delay time. If you just want small delays, I would use a long carry-chain since there is no routing delay between the carry-elements and you can control the delay amount a little by deciding where to tap-off the carry-chain. Still you have variations on the delay due to temp/volt/process corners.

If you don't care about the delay time (which sounds weird to me), you can force placements on primitives by RLOCing them. You have to instantiate the primitives in your HDL and give the RLOC values. With VHDL you can create a "for generate loop" which would place an arbitrary number of these primitives. These primitives will not be touched by the synthesize tool or the PAR tools.

Göran Bilski

Unless you talking about very long time (> a few ns) which would be very hard to do

As Antti has said, this is a thoroughly bad idea.

But if you really, really must.... send the signal out through a pad, and back in through a different pad (having linked the two pads together with an external wire, of course). Choosing the right I/O standard and drive characteristics gives you a limited amount of control over the delay; and because it's going out of the part, the optimizer won't take anything away.

It's still a rubbish thing to do, though. How much delay? Can you get the desired effect with phase-shifted clock from a DCM?

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First, thank for all your answers, in facts, I'm designing an emulator for an hardware microcontroler. So I've to embed microcontroler sources ( originaly coded for hardware IC design ) in my virtex FPGA. One of the goal of the project is to preserve microcontroleur functionality and mechanisms ( to obtain a real emulation ), this why I can't use a clock to delay my signal. This signal must be delayed by about 50ns. I know this is a large time without use of clock, and that's all my problem..

best regards, Michel Talon.

...or, if you don't like wire, you can use an unbonded IOB. Send a signal to the IOB's output pin and get the signal back from the same IOB's input pin with the IDELAY turned on. No wire required! I would never do this though. Ahem! HTH, Syms. p.s. You don't _have_to use an unbonded IOB, but it saves worrying about what might be connected to it.

First, thank for all your answer, In fact I'm designing an emulator for an onchip microcontroler. The goal of the project is to obtain the same mecanisms and functionality for the emulator to reach a real emulation. I've to carry microcontroler IC design sources to virtex FPGA without modify them or just a little. The signal I've to delay is embedded in one of the lowest hierarchical module and I can't input a clock to this module. The signal must be delayed by 20ns minimum, but accuracy is not required.

I know this is not a good thing for FPGA, but I've not better solution, and this all my problem..

Thank,

Best regards, Michel Talon.

Sounds like you are on a totally wrong path if you are trying to emulate datasheet timing this way... What is it so special about this signal that it can't be clocked out?

/Mikhail

This is another case of an incomplete or imprecise question: If (for whatever strange reason) a 20 ns delay is needed, the only realistic way to do that is to run the signal out of the chip and back into it, with a low-pass filter in-between, like 1 kilohm resistor and

20 pF capacitor to ground, or 510 Ohm and 47 pF. Why anybody wants to do this rema>

FPGAs themselves are not designed to give time-delays. If this is an important emulation detail (and there may be others, too ) I'd suggest you add an external delay block. An LVC14 Schmitt, and R/C elements, which can be series, or shunt, connected. Depends on the nature of the delay.

Another approach would be to start with a much faster clock than the core needs : Divide it down for the core, and use the finer granularity for clocked delays on the pins that need the 'emulation patches'. eg 100Mhz will allow you 10ns IO granularity, and 100Mhz local clock speed is lowish for modern FPGAs. This will also simulate correctly.

-jg

If this is a 'don't touch' exercise, then you will need the external delay patch I mentioned in my other post. You probably should also try and get similar-process external IO buffers if you are looking for accurate emulation.

-jg

...but they're very proficient at it when you don't want them to be! :-) Cheers, Syms.